About
Well-funded deep tech company building a new compute paradigm based on photonic AI accelerators. The team works across hardware, compiler, and runtime development, with performance modelling central to hardware–software co-design.
This role focuses on developing accurate simulation models that inform chip design before fabrication.
What you'll do
- Develop cycle-accurate performance models for next-generation AI accelerator architectures
- Build and maintain detailed simulations using SystemC, gem5, or similar frameworks
- Model compute, memory, and interconnect behaviour under realistic ML workloads
- Identify architectural bottlenecks and provide quantitative guidance to hardware teams
- Partner with compiler and runtime engineers to validate assumptions
- Translate simulation results into actionable design recommendations
What you'll need
- Experience with cycle-accurate modelling and architectural simulation
- Hands-on expertise with SystemC and/or gem5
- Deep understanding of computer architecture and memory systems
- Experience modelling AI or HPC workloads
- Strong C++ skills and comfort working close to hardware abstractions
- Interest in hardware–software co-design and cross-layer optimisation
Shortlisted candidates will be contacted within 48 hours.
